It is common practice in electronic packaging to provide carrier structures with enhanced heat dissipation characteristics to assist in the cooling of attached components and subassemblies. With specific emphasis on chip on flex (COF) and chip on board (COB) packaging used for direct attach of integrated circuit chips to a variety of carriers including flexible polyimides, glass reinforced epoxy (FR4), and ceramic circuit carriers, a structure which provides not only enhanced heat dissipation, but also added ground or electrical shielding characteristics is generally provided using two techniques.
The first technique involves directly affixing integrated circuit chips to metal heatsinks that are bonded or laminated to the circuit carriers. In these applications, wirebonded chips are generally attached to the metal heatsinks with epoxy based adhesives that may contain incorporated electrically conductive particles and/or thermally conductive particles to reduce thermal resistances of chip-heatsink interfaces. The second technique involves directly affixing integrated circuit chips to circuit carrier surfaces possessing chip attach pad locations that are electrically and thermally interconnected by metal filled or plated vias to large metal ground or shielding planes present within or on the opposing side of the circuit carrier.
Although direct chip attach (DCA) to either heatsink structure provides an effective solution for both heat dissipation enhancement and rudimentary electrical isolation, the adhesives used to affix chips to heatsinks or carrier surfaces are not readily reworkable. Therefore the vast majority of electrical, manufacturing assembly, and test losses associated with the chip assembly are non-recoverable. These yield detractors encompass known good die (KGD) issues and most common DCA assembly and manufacturing process flow defects including adhesive overflow onto bond pads, misoriented die, mechanically damaged die, wirebond pattern recognition errors, and wirebond sweeps, as well as other bond and post-bond test introduced defects. For single chip packages these yield losses can usually range to several percent, while yield losses in multi-chip assembly configurations can range to 30% or more depending on the assembly complexity. Given the aggregate potential for assembly yield loss coupled with the high volume manufacturing requirements associated with assembly of most packages that rely on chip on flex (COF) and chip on board (COB) technologies (typically 1,000 to 100,000 per week), it is clear that significant cost savings could be realized by the development and implementation of a simple and cost effective DCA to heatsink packaging structure that supports chip rework and replacement.
A resolution to the above problems is found in the application of the techniques of U.S. patent application Ser. No. 08/349,854, filed Dec. 6, 1994, and entitled REWORKABLE ELECTRONIC APPARATUS HAVING A FUSIBLE LAYER FOR ADHESIVELY ATTACHED COMPONENTS, AND METHOD THEREFOR and U.S. patent application Ser. No. 08/530,452, filed Sep. 19, 1995 and entitled METHOD AND SYSTEM FOR REWORKABLE DIRECT CHIP ATTACH (DCA) STRUCTURE WITH THERMAL ENHANCEMENT, both assigned to the assignee of the present Patent Application. The use of a layer of fusible material, such as solder, enables the adhesive or cement that bonds the chip to the carrier to be removed with the chip. This avoids the necessity to scrape, grind or abrade the carrier location of chip attachment to remove residual cement or adhesive. Accordingly, the difficulty, cost and added part loss occasioned by the residual cement removal procedure are avoided.
Although these solutions are a resolution of the problem, the application of heat is required to effect the separation. The temperature must be great enough to soften the fusible material sufficiently to release the chip from the carrier while not being high enough to damage the electronics on either the chip or the carrier. Although the procedure can be practiced within manageable temperature ranges, the reworking would be expedited if the process of separation could be effected directly without the imposition of an elevated temperature.
When the carrier used is a heatsink, the heat dissipation characteristics make the application of heat more critical and the margin for error more limited. In this environment, an alternative to the process of heating the assembly would be of even greater benefit. A more direct means for separating the chip from the remainder of the assembly would not only simplify the process, but also reduce the incidence of heat or mechanical damage that reduce the yield of reworked assemblies.
Further cost benefits could be achieved if the cured adhesive attachment of the direct attach device could be wholly eliminated. The adhesive application and cure processes are time consuming and expensive, and can account for a significant portion of the manufacturing assembly costs of small form factor packages. For example, the adhesive dispense and cure operations required for conventional direct chip attach on arm electronics cables such as those used in state of the art small rigid disk drive products can encompass approximately 25 percent of the total component subassembly cost. Moreover, as previously discussed, once the epoxy adhesive is cured, rework/repair or replacement of defective chips or chip site defects is not cost effective. Therefore, the development of an economical chip attach structure and assembly process that is both reworkable and provides for elimination of costly and time consuming adhesive processing steps is of great economic value to industries that provide high volume form factor packaging of electronic assemblies.
A still further problem associated with electronic assemblies used in particular environments is the compactness required to meet the requirements of specific applications. For example, flexible circuitry and card electronic assemblies used in rigid disk data storage devices, telecommunications equipment, portable computers, computer peripherals, and a host of consumer electronics generally require high density packaging of components and compact efficient electronic carrier integration in form factor packages. The physical constraints within the various form factor designs in many of these packaging applications restricts both area and height available for electrical carrier wiring component placements, device interconnections, and carrier attach within form factor housings. The limited three dimensional space available for the electronics usually drives one or more forms of packaging minimization including the use of thin, flexible carrier materials with fine line/space/via wiring, small passive discrete components and various direct chip attach technologies to support integration and placement of silicon devices include wirebonded chip on flex and wirebonded chip on board attach methods. However, in addition to providing for space savings, the packaging design and assembly methods must also support high volume, low profit margin manufacturing, since the bulk of high density form factor packaging is used in low cost consumer electronics applications.
Unfortunately, low cost manufacture of form factor electronics using direct chip attach technology is inherently difficult, since most all direct chip attach processes and package structures are relatively expensive to produce, as manufacturing requires multiple steps with specialized equipment,, and slow throughput batch assembly steps involving chip adhesive and/or encapsulant application and cure steps. Moreover, additional cost is usually incurred from assembly fallout due to inability to test for known good chips and from inability to rework many direct chip attach structures in use today. Additionally, the many steps requires for direct chip attach assembly, ultimate manufacturing cost, yields, and subsequent integration of direct chip attach carrier assemblies into the form factor packages are also highly dependent on the application specific carrier package designs.